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Logic 2 - Ideas and Feature Requests


Voters 13

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13

Bus Analyzer - Decode on Digital Transitions

A
 Anonymous

I would be good to have a possibility to group signal as bus and display them next to signal channel.

  • 27-02-2020 -
A

Activity Newest / Oldest

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Tim

(#81069)
"I have 3 digital signals which indicate 1 of 8 different states (000, 001, 010, ...,111).
Do you have any extensions which allows these 8 states to be displayed automatically?
It's a pretty basic function, but without it I am wasting a lot of time checking for the correct combinations of 3 waveforms.
It's tedious!"

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Tim

discuss.saleae.com/t/combine-multiple-bits-of-state-machine-digital-signals-and-have-text-on-screen/1684

"Could you help me to put text(e.g. IDLE) on the GUI depending on some digital bits as shown in picture in purple color? I am ok with any solution like combining signals and have a single bus
Which tool shall I use to achieve this?

Example: When
state_bit_1 , state_bit_0 = “00” then I would like to have a text “IDLE”
state_bit_1 , state_bit_0 = “01” then I would like to have a text “PREPARE” "

A

allen

I have updated the old analyzer found here: github.com/Zweikeks/saleae-logic-SimpleParallelNoClock-Analyzer to work with version 2. To get it to analyze the data you may have to reset the analyzer to get the data. The updated analyzer is here: github.com/ablaylock/SimpleParallelNoClock

D

David

git clone --recursive github.com/ablaylock/SimpleParallelNoClock
...
[SimpleParallelNoClock]$ python build_analyzer.py
Running on Linux
Traceback (most recent call last):
File "/home/djg/saleae/SimpleParallelNoClock/build_analyzer.py", line 37, in
os.chdir( "source" )
FileNotFoundError: [Errno 2] No such file or directory: 'source'

My git clone and browsing online don't show a source directory.

Am I missing something or is the github repo missing files?

Another vote for built in grouping and displaying as one item like other analyzers I have used.

A

allen

I pushed the source directory. I agree that a grouping and more a official implementation would be significantly better.

N

Nicolas

Seems there is still no progress.
Will check by in 6 month.

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Tim

discuss.saleae.com/t/show-bus-value/1001/3
"Normally on devices I’ve used you can just group bits into a bus on the display. Implemented as an analyzer in your software, I think you could simply make a different parallel mode that is sensitive to rising/falling edges on all data bits."

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Tim

Unfortunately (and quite bit surprisingly), we don't have a way of decoding this simple case.

Currently, our pre-installed analyzers will decode messages via the following methods:

1. via a clock signal
2. via a asynchronous signal (no clock) using a specified baud rate

What's missing is a way to decode messages upon digital channel transitions.

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Tim

Merged with: Analyzer that Decodes on Digital Transitions

K

Keegan

FYI There was a very similar request here: ideas.saleae.com/b/feature-requests/bus-display/

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Tim

Thanks! I missed that one. I'll go ahead and merge this into that.

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Tim

discuss.saleae.com/t/show-bus-value/1001/2
"Hello, we purchased this logic pro 16 intending to log the value of an 8 bit microcontroller port over time. A new value is written to the port when the state changes.

I assumed that either we can group the digital lanes into a bus, or else use the parallel decode option. However I see no capability to display a bus and the parallel decode option requires a clock.

This is a rudimentary logic analyzer function. Is there an option hiding somewhere?"

M

Mitch

Yes, a "poor man's, Simpler, Parallel" analyzer, will produce bus values for every sample, without dependence on a clock signal. But also a great way to view the combined bus signals in the waveform window area. Just like Cadence can do inside Simvision. They call it "Grouping". The way they do it, you can group arbitrary bit traces together to form such a bus view.

S

stephane

It will be good to have the same unofficial LLA (github.com/Zweikeks/saleae-logic-SimpleParallelNoClock-Analyzer), but for the version 2.3.19
BR

N

Nicolas

Would be relly interresting to get this basic one

J

JEAN VISCONTE

And of course allow HLAs to manage this bus data